Semiconductor packaging has evolved from traditional 1D PCB designs to cutting-edge 3D hybrid bonding at the wafer level. This advancement allows interconnect spacing in the single-digit micron range, with bandwidths of up to 1000 GB/s, while maintaining high energy efficiency. At the core of advanced semiconductor packaging technologies are 2.5D packaging (where components are placed side by side on an intermediary layer) and 3D packaging (which involves vertically stacking active chips). These technologies are crucial for the future of HPC systems.
2.5D packaging technology involves various intermediary layer materials, each with its own advantages and disadvantages. Silicon (Si) intermediary layers, including fully passive silicon wafers and localized silicon bridges, are known for providing the finest wiring capabilities, making them ideal for high-performance computing. However, they are costly in terms of materials and manufacturing and face limitations in packaging area. To mitigate these issues, the use of localized silicon bridges is increasing, strategically employing silicon where fine functionality is critical while addressing area constraints.
Organic intermediary layers, using fan-out molded plastics, are a more cost-effective alternative to silicon. They have a lower dielectric constant, which reduces RC delay in the package. Despite these advantages, organic intermediary layers struggle to achieve the same level of interconnect feature reduction as silicon-based packaging, limiting their adoption in high-performance computing applications.
Glass intermediary layers have garnered significant interest, especially following Intel's recent launch of glass-based test vehicle packaging. Glass offers several advantages, such as adjustable coefficient of thermal expansion (CTE), high dimensional stability, smooth and flat surfaces, and the ability to support panel manufacturing, making it a promising candidate for intermediary layers with wiring capabilities comparable to silicon. However, aside from technical challenges, the main drawback of glass intermediary layers is the immature ecosystem and current lack of large-scale production capacity. As the ecosystem matures and production capabilities improve, glass-based technologies in semiconductor packaging may see further growth and adoption.
In terms of 3D packaging technology, Cu-Cu bump-less hybrid bonding is becoming a leading innovative technology. This advanced technique achieves permanent interconnections by combining dielectric materials (like SiO2) with embedded metals (Cu). Cu-Cu hybrid bonding can achieve spacings below 10 microns, typically in the single-digit micron range, representing a significant improvement over traditional micro-bump technology, which has bump spacings of about 40-50 microns. The advantages of hybrid bonding include increased I/O, enhanced bandwidth, improved 3D vertical stacking, better power efficiency, and reduced parasitic effects and thermal resistance due to the absence of bottom filling. However, this technology is complex to manufacture and has higher costs.
2.5D and 3D packaging technologies encompass various packaging techniques. In 2.5D packaging, depending on the choice of intermediary layer materials, it can be categorized into silicon-based, organic-based, and glass-based intermediary layers, as shown in the figure above. In 3D packaging, the development of micro-bump technology aims to reduce spacing dimensions, but today, by adopting hybrid bonding technology (a direct Cu-Cu connection method), single-digit spacing dimensions can be achieved, marking significant progress in the field.
**Key Technological Trends to Watch:**
1. **Larger Intermediary Layer Areas:** IDTechEx previously predicted that due to the difficulty of silicon intermediary layers exceeding a 3x reticle size limit, 2.5D silicon bridge solutions would soon replace silicon intermediary layers as the primary choice for packaging HPC chips. TSMC is a major supplier of 2.5D silicon intermediary layers for NVIDIA and other leading HPC developers like Google and Amazon, and the company recently announced mass production of its first-generation CoWoS_L with a 3.5x reticle size. IDTechEx expects this trend to continue, with further advancements discussed in its report covering major players.
2. **Panel-Level Packaging:** Panel-level packaging has become a significant focus, as highlighted at the 2024 Taiwan International Semiconductor Exhibition. This packaging method allows for the use of larger intermediary layers and helps reduce costs by producing more packages simultaneously. Despite its potential, challenges such as warpage management still need to be addressed. Its increasing prominence reflects the growing demand for larger, more cost-effective intermediary layers.
3. **Glass Intermediary Layers:** Glass is emerging as a strong candidate material for achieving fine wiring, comparable to silicon, with additional advantages such as adjustable CTE and higher reliability. Glass intermediary layers are also compatible with panel-level packaging, offering the potential for high-density wiring at more manageable costs, making it a promising solution for future packaging technologies.
4. **HBM Hybrid Bonding:** 3D copper-copper (Cu-Cu) hybrid bonding is a key technology for achieving ultra-fine pitch vertical interconnections between chips. This technology has been used in various high-end server products, including AMD EPYC for stacked SRAM and CPUs, as well as the MI300 series for stacking CPU/GPU blocks on I/O dies. Hybrid bonding is expected to play a crucial role in future HBM advancements, especially for DRAM stacks exceeding 16-Hi or 20-Hi layers.
5. **Co-Packaged Optical Devices (CPO):** With the growing demand for higher data throughput and power efficiency, optical interconnect technology has gained considerable attention. Co-packaged optical devices (CPO) are becoming a key solution for enhancing I/O bandwidth and reducing energy consumption. Compared to traditional electrical transmission, optical communication offers several advantages, including lower signal attenuation over long distances, reduced crosstalk sensitivity, and significantly increased bandwidth. These advantages make CPO an ideal choice for data-intensive, energy-efficient HPC systems.
**Key Markets to Watch:**
The primary market driving the development of 2.5D and 3D packaging technologies is undoubtedly the high-performance computing (HPC) sector. These advanced packaging methods are crucial for overcoming the limitations of Moore's Law, enabling more transistors, memory, and interconnections within a single package. The decomposition of chips also allows for optimal utilization of process nodes between different functional blocks, such as separating I/O blocks from processing blocks, further enhancing efficiency.
In addition to high-performance computing (HPC), other markets are also expected to achieve growth through the adoption of advanced packaging technologies. In the 5G and 6G sectors, innovations such as packaging antennas and cutting-edge chip solutions will shape the future of wireless access network (RAN) architectures. Autonomous vehicles will also benefit, as these technologies support the integration of sensor suites and computing units to process large amounts of data while ensuring safety, reliability, compactness, power and thermal management, and cost-effectiveness.
Consumer electronics (including smartphones, smartwatches, AR/VR devices, PCs, and workstations) are increasingly focused on processing more data in smaller spaces, despite a greater emphasis on cost. Advanced semiconductor packaging will play a key role in this trend, although the packaging methods may differ from those used in HPC.
Post time: Oct-07-2024